CW308 GPIO always pulled low

Hi,

I have problems getting nonzero values from
print(scope.advancedSettings.cwEXTRA.readTIOPins())
and
print(scope.advancedSettings.cwEXTRA.readTIOPin(3))
when I use the CW308 Board with CW Lite.
I connected the VCC3.3V pin(on J11) to GPIO3, and to VREf on J7. J4 is set to TVRef(victim supplies the reference). At least system ground and CW capture 3.3V(pin3) is connected to the board on J1. I tried the whole 20pin connector also on J1, without success
The above conditions should allow me to get a constant true reading on gpio 3, I thought.
The remaining HW config:
J3 → HS2/OUT
Ext DC switch → auto
J16 → all 3 pins floating
J14 → set to victim board(default)
All LDO switches are set to J1/CW. Vadj is set to 3.3V(but I don’t think Vadj has any relevance in this case)

I have configured the CW Lite with the following settings:
from collections import namedtuple
Range = namedtuple(‘Range’, [‘min’, ‘max’, ‘step’])
scope.glitch.clk_src = “clkgen”
scope.glitch.output = “glitch_only”
scope.glitch.trigger_src = “ext_single”

width_range = Range(10, 30, 0.4)
offset_range = Range(-20, -2, 0.4)
ext_range = range(1, 1000)

scope.glitch.width = width_range.min
scope.glitch.offset = offset_range.min
scope.glitch.repeat = 1
def glitch_on(scope):
#scope.io.glitch_lp = False
#scope.io.glitch_hp = True
scope.io.glitch_lp = True
scope.io.glitch_hp = False
def glitch_off(scope):
#scope.io.glitch_hp = False
scope.io.glitch_lp = False
glitch_on(scope)
scope.glitch.ext_offset = 0
print(scope.glitch)

#help(scope)
print(scope.clock.clkgen_freq)
print(scope.clock.freq_ctr_src)
scope.clock.freq_ctr_src = “clkgen”
print(scope.clock.freq_ctr_src)
print(scope.clock.freq_ctr)
scope.io.tio1 = “high_z”
scope.io.tio2 = “high_z”
print(“”)
print(scope)
#print(scope.extra.readTIOPin(1))
scope.advancedSettings.cwEXTRA.readTIOPins()

Got the result:

clk_src = clkgen
width = 10.15625
width_fine = 0
offset = -19.921875
offset_fine = 0
trigger_src = ext_single
arm_timing = after_scope
ext_offset = 0
repeat = 1
output = glitch_only

7384615.384615385
clkgen
clkgen
7384620

cwlite Device
gain =
mode = high
gain = 30
db = 24.8359375
adc =
state = False
basic_mode = rising_edge
timeout = 2
offset = 0
presamples = 0
samples = 5000
decimate = 1
trig_count = 332953391
clock =
adc_src = clkgen_x4
adc_phase = 0
adc_freq = 29538459
adc_rate = 29538459.0
adc_locked = True
freq_ctr = 7384620
freq_ctr_src = clkgen
clkgen_src = system
extclk_freq = 10000000
clkgen_mul = 2
clkgen_div = 26
clkgen_freq = 7384615.384615385
clkgen_locked = True
trigger =
triggers = tio4
module = basic
io =
tio1 = high_z
tio2 = high_z
tio3 = high_z
tio4 = high_z
pdid = high_z
pdic = high_z
nrst = high
glitch_hp = False
glitch_lp = False
extclk_src = hs1
hs2 = clkgen
target_pwr = True
glitch =
clk_src = clkgen
width = 10.15625
width_fine = 0
offset = -19.921875
offset_fine = 0
trigger_src = ext_single
arm_timing = after_scope
ext_offset = 0
repeat = 1
output = glitch_only

0

Calling print(scope.advancedSettings.cwEXTRA.readTIOPins()) or the precise pinreadTIOPin() afterwards doesn’t help either.
I measured the pins with a multimeter, and they were about 1,1V, with GPIO3 about 1,3V at the J1 pin number 14. Of course it was 3.3V at J5 pin 9.
I suspect the diode clamps mess up the gpio value, but I don’t know how to correct this. J4 aka Vref setting is done.
Do you have any idea what could be done to get the pins out of pull-down?

Best regards,
Norbert

Hi Norbert,

Reading the IOs requires a new ChipWhisperer FPGA bitfile, see details here:

Jean-Pierre

I tought I would get some kind of error if the FPGA was unable to process the request properly.
Nevertheless, this solves the problem. Thank you.
So the pull down was caused by the CW Lite side of the J1, instead of the UFO board.