Hi,
I have been looking into the CW code to better understand what is happening. It took me a while to understand how SAM3U,The FPGA and ACD and such are working together (and how the code interfaces).

I will do more documentation(or is it already somewhere?) but for the record/please review
The python code uses a custom protocol to talk (via libusb) to the SAM3U chip
The SAM3U chip runs firmware (firmware hardware/capture/chipwhisperer-lite/sam3u_fw) with some functionality:
The FPGA chip is programed mostly in verilog (hardware/capture/chipwhisperer-lite/hdl hardware/common and
openadc/hdl/example_targets) using makeise.
Something like that?
I also watched http://scanlime.org/ 's nice video on glitching usb and was wondering is the FPGA would not be able to directly generate those few usb messages?
I have been looking into the CW code to better understand what is happening. It took me a while to understand how SAM3U,The FPGA and ACD and such are working together (and how the code interfaces).

I will do more documentation(or is it already somewhere?) but for the record/please review
The python code uses a custom protocol to talk (via libusb) to the SAM3U chip
The SAM3U chip runs firmware (firmware hardware/capture/chipwhisperer-lite/sam3u_fw) with some functionality:
- Programming the FPGA
Doing target UART -> USB protocol translations(signal go through the FPGA)
Programming the AVR target (signal go through the FPGA)
Pumping the ACD data out of the FPGA to the PC
But mostly talking to the FPGA over a large bus
The FPGA chip is programed mostly in verilog (hardware/capture/chipwhisperer-lite/hdl hardware/common and
openadc/hdl/example_targets) using makeise.
- It works mostly as as tmuxing device (passing data depending on a few register settings)
Does clock generation (using DMC's)
Has a few registers (muxing/routing)
Configuration of tiggers/routing of clogs
Configuring openADC like Using internal/external clock for the ADC
Something like that?
I also watched http://scanlime.org/ 's nice video on glitching usb and was wondering is the FPGA would not be able to directly generate those few usb messages?
Last edited by ExMachina on Mon Jul 17, 2017 4:45 am, edited 1 time in total.