Discussions of performing power analysis, techniques, implementations, etc. Does not need to use ChipWhisperer.
#1019 by aliakbarp
Mon Nov 21, 2016 2:49 am
Hi Colin,

I am currently using Sasebo-GIII (Sakura-X) to do the experiment of SCA.
The maximum frequency of spartan-6 is 24MHz. However, I can only modify the frequency up to 12MHz by divide by 2 in the Verilog code. The error will prompt if it is devided by one. Is there any other way to use 24MHz by modifying the Verilog code?
In addition, the web address (http://avrcryptolib.das-labor.org.) you mentioned in your paper (Synchronous sampling and clock recovery of internal oscillators for side channel analysis and fault injection) does not exist anymore. May I request the AES implementation in C (128 and 256 version)
Thank you so much man.

Regards, :D :D :)

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