ADC Clock questions

This is my understanding of the ADC clock, please let me know if it is incorrect.
Also some questions included :slight_smile:

The ADC clock can accept input from extclk or clkgen output. When receiving from extclk, it can do so directly without passing through the DCM. What is the point of going directly vs going via the DCM with a 1x multiplier? To reduce latency?

Thinking some more about this and my previous clkgen questions, does the flow go:
extclk|clkgen --> dcm --> adc clock input?
So is the DCM just for multiplying the input clock signal?

There seems to again be a frequency measuring signal for the resultant adc clock. Is that what the ADC Freq is? A measurement of the clock provided to the adc?

I assume the Phase Adjust is applied to the adc clock last, just before the adc receives it. Is this -255 to 255 value a constant adjustment value? Or it is based on the clock, like some small percentage of the frequency?

Again what are the “Reset ADC DCM” and “DCM Locked” operations for?

The DCM block provides the ability to nudge the phase slightly. This provides a very small (<5nS) offset, you’d have to check the Spartan 6 datasheet for details but it’s effectively a constant delay. The idea of this is to nudge your sample points off the edge of clock edges if required. It is a very small delay though so at lower frequencies it’s not as useful.

This is basically the advantage of the DCM block vs. going direct with the 1x clock. Note that if your device clock is varying you might have to go direct, as when the input clock to the DCM changes this can cause it to become unlocked. When the block is unlocked it no longer has a proper phase/frequency relationship, and must be ‘reset’ before it will become locked back.

This description of the clock system might be useful: assembla.com/spaces/openadc … ing_System

The “ADC Freq” is indeed a measure of the ADC clock frequency. It’s there to give you a ‘sanity check’ that you’ve configured the clock system correctly… i.e. the blocks are locked, dividers set properly, etc.

Ah thanks Colin, that wiki link is exactly what I was after.
I forgot about the wiki. I was looking through the cw docs and the python code and piecing it together from hints in them :slight_smile:

yeah it’s all a bit jumbled now - again part of this came from my desire to separate the ADC capture side into a stand-alone project, so then I end up with these very important details not as obviously available from the ChipWhisperer side! let me know if stuff seems wrong too :wink:

These questions refer to the diagram you posted in a previous reply:

What is the purpose of the “Clock Synthesis (CLKGEN)” part of the diagram?

What section does the clock multiplication? The divider or the Clock Synthesis?

When using the command to read back the extclk/clkgen frequency, if you are reading the clkgen frequency then what point of that diagram would it come from?

Initially I would have thought that the “Clock Synthesis” part of the diagram did the div and mul. However that diagram makes it appear to not be the case.

Sorry on the delay - somehow missed this post. The “CLKGEN (Synthesis)” does the multiplication + division. It has a programmable mul/div that forms the entire clock synthesis. The other block labelled “CLKGEN (Divider)” is actually not programmable right now - it was originally designed to allow you to further divide the CLKGEN frequency before sending out a port pin. It’s currently bypassed however, so your CLKGEN output is the IO pin output frequency.

The CLKGEN frequency is the output of the “CLKGEN (Synthesis)” block. Sorry for the confusion!