I’ve build a new project in Vivado, copied all verilog files from spartan6 project, and created a new constrains file with pin mappings.
I used available PMOD header for clk_in, uart_tx, uart_rx and trigger.
The hardest part was to find pin suitable for clock line. I used package view in Vivado and I was checking all pins connected to pmods. For SP701 it’s PMOD3.
Then I used jump wires to connect it to chipwhisperer.
I’ve configured FPGA via JTAG.