CW-lite IO glitching

1

Hi everyone,

I am trying to glitch a target with uboot into the shell.

Using the vcc pin and glitch output I can glitch during boot but always getting a system halt with a message to reboot the system.

I did notice that when grounding the clock pin at a specific time the system will halt too. Grounding the clock pin for 0.5s.

It seems that I can not use the glitch pin for this long period.

So I would like to use one of the io pins to drive the clock pin to gnd. But this most likely will not work as accurately. Can I specify clock cycles to wait till changing io pin status. And also have the io pin low for specified clock cycles or millisecond?

Thanks for the help.

2

Hi,

Something like that should be possible, but you’ll need to modify and rebuild the FPGA bitstream: chipwhisperer/hardware/common/hdl at develop · newaetech/chipwhisperer · GitHub and chipwhisperer/hardware/capture/chipwhisperer-lite/hdl at develop · newaetech/chipwhisperer · GitHub. You can build with Xilinx ISE

Alex

3

Hi Alex,

Thanks for the reply. I did find another solution. To extend the trigger repeat I just stacked manual triggers. The timing is a problem though because it is not coupled with the clock.

-e