Answered here:
As the notebook says, “We’re only capturing 129 samples (the minimum allowed), and the encryption is completed in less than 60 samples with an x4 ADC clock. This makes sense - as we mentioned above, our AES implementation is computing each round in a single clock cycle.”
In case you haven’t noticed, there is a basic simulation testbench that you can run to see exactly what the target does: https://github.com/newaetech/chipwhisperer/tree/develop/hardware/victims/cw305_artixtarget/fpga/vivado_examples/aes128_verilog/sim
Go there and run:
make DUMP=1
gtkwave aes.gtkw&
(you may need to install gtkwave and iverilog, which is easily done on Ubuntu with apt install ...)
You will see that the AES encryption is done in 11 clock cycles.
This attack doesn’t require knowledge of what is happening on which clock cycle; you just need to ensure that you are capturing the portion of the AES encryption that is targeted by the attack (in this case, the last round). Beyond that, the attack doesn’t require knowledge of how long the encryption takes.
Jean-Pierre