Hello everyone, I try to make some tests on my implementations for the new AES styles described, and I would like to introduce a fault glitch to see how this technique impacts my system. My target is S6LX9 uses in programming FPGA by Xilinx.
How I can do this type of analysis?
You should be able to glitch this target exactly the same as your would a microcontroller - setup a trigger at the start of AES so we know when to glitch, and record the result of the encryption. If it’s incorrect, you’ve glitched the target.
Alex