Sorry for the delay.
Indeed I’ve been working on 3 implementations of masked/bitsliced AES for Cortex-M:
- the one from ANSSI that Alex mentioned,
- the one from “knarfrank”: https://github.com/knarfrank/AES-128-ARM-Cortex-M0
- the one from Sebastien Riou: https://github.com/sebastien-riou/masked-bit-sliced-aes-128
The two implementations from ANSSI (the one for AVR and the one for Cortex-M4) have configurable masks (AVR expects 2 configuration bytes followed by 16-byte mask and ARM implementation expects either 16-byte or 32-byte mask). The other 2 implementations generate the mask internally using an RNG and I’m trying to keep the implementations upstream as pristine as I can. In the case of a “real” target, the mask wouldn’t be known anyway.
To support all this, I started a series of PR on Gtihub. The first one is there to support variable length commands, which is required for setting the masks.
Once this is merged, I’ll create more pull requests to add the implementations into the firmware directory.
The last two implementations requiring a change in the HAL to start the platform RNG as well as having a get_rand(), they won’t be supported by all platforms yet (I’ve worked on and tested K82F, nRF52840 and STM32F4 so far).
For the experiments I’m running I started maintaining a repository of pre-compiled firmware for the simpleserial_aes program: https://github.com/jmichelp/chipwhisperer-firmware
I need to finish a few commits and I’ll recompile them soon (the RIOU and KNARFRANK implementation were broken when I last compiled them).