Synchronize Target and Chip Whisperer Clock

Hello i´m working with the Chip Whisperer Lite and i´ve broken off the arm target and connected my own target. I want do some voltage glitching in “ext_single” and “glitch_only” mode. I don´t use the serial communication, i only set the trigger high/low and show glitch results by setting some GPIO´s from my target high/low and check them on the chip whisperers IO pins.

To synchronize the clock i only can use an output pin of my target where it´s clock is provided (48MHz) and route it to HS1/I, i have no way to transfer the clock (HS2/O) from the chip whisperer to the target.
Now i have set scope.glitch.clk_src from the glitch module to “target”.

Is it necessary that i change the clock of the adc (scope.adc.clkgen_src) to “external” as well or can i use the “system” clock (96MHz)?

Can it cause problems if the target gets glitched (voltage glitch) and i use the clock of it for the chip Whisperers adc and glitch module?

Thank you again for you´re great support and best regards Rik

It’s not necessary but it’s definitely recommended. If you use the system clock, even if the frequencies are the same or related, jitter and small differences between the two clock sources means you’re no longer sampling synchronously. There’s no reason not to use “external” (except as noted below).

I suppose that if you glitch the target hard enough it’s possible that you’ll disturb its clock. There’s only one way to find out! Depending what happens to the clock, it’s possible that this could mess up power sample acquisition. However if you use extclk_x1 or extclk_x4, then the target clock goes through a PLL on the FPGA and so it may get sufficiently cleaned up. There’s no way to know that other by inferring from observed behaviour. If the clock does get nasty in a way that appears to mess up your power measurements, then that would be the reason to not source the ADC sampling clock from the target. Just be aware that you’re no longer sampling synchronously.
I hope this helps,

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