Some background details:
I am trying to implement a Template attack on a microprocessor using 2 FPGA’s:
1 - SPARTAN-6 which is connected to my laptop and also to the probe.
2 - Xilinx which is connected to the victim device and also to the internet. (i cannot change this setup)
The Xilinx, which is the server, listen to some port until he get a scan pattern. then he insert the pattern to the
victim device and wait until the device is done. After that the Xilinx sent back to the client that the device has done running the pattern.
From my laptop i open socket (has a client) and connect to the Xilinx, then i generate the pattern and sent it to Xilinx and wait until the victim device is done. Meanwhile i am using the SPARTAN-6 to capture the power traces of the victim device using the probe.
I am connect to SPARTAN-6 using the virtual machine.
Since the SPARTAN-6 does not connect to the victim device and i sent the pattern to Xilinx, how can i
use the cw.capture_trace(scope, target, text, key) without giving a target, text and key.
i.e i just need the SPARTAN-6 to capture the power traces.
how can i control the capture time? (lets say i need it to capture a trace of 3 sec long).