What's propose of J5 on CW-Lite

I’ve found J5 on the CW-lite diagram:

How I can use it?
What’s propose of that pins?

Looking at the FPGA code here, these are signals that relate to the SPI flash (U9) that is not mounted.


As J-P mentioned you can use this freely - it does’t have a “use” per-say. This would need you to rebuild the FPGA etc… those were basically just spare signals routed out during the internal development, so there is no “normal” use of them.

Thanks Jean-Pierre and Colin,

Do you think I could use it to off load internal storage for samples? For example use it as SDIO or even simple passthrough to other FPGA?


Slow response as missed this sorry - yes you could! I think there was 9 pins routed out so you could do 8x data + clock for example.

Are you working already on something like that? Or did you plan it?