The glitch repeat count limit of 255 is too low for my target and I would like to increase it.
I have just changed the limit and of course hit a problem. In the code below, rest[6] is only a byte and setting anything bigger that 255 is not possible.
What I’ve seen is 255 repeat is enough. Like in my target if I set anything larger than 204 it would basically reset or hang the system. My target is running at 204Mhz so 204 repeat cycles is 1us glitch window. 204 cycles translate to maybe 100 ARM instructions.
You might want to remove some of the capacitors on your cpu core power rail to make it easier to glitch.
I was looking into that code today so I figured I post something about this.
There is a direct relation between the code here and the FPGA code. github.com/newaetech/chipwhispe … ch.py#L345
The code reads a register (8 bytes) and modifies byte 7 to insert the Repeat
@setupSetParam("Repeat")
def setNumGlitches(self, num):
"""Set number of glitches to occur after a trigger"""
num = int(num)
resp = self.oa.sendMessage(CODE_READ, glitchaddr, Validate=False, maxResp=8)
if resp is None or len(resp) < 8:
logging.warning('Glitch Module not present?')
return
if num < 1:
num = 1
resp[6] = num-1
self.oa.sendMessage(CODE_WRITE, glitchaddr, resp, Validate=False)