Hello everyone,
I’m currently working on implementing a test CW-husky with the NAE-CW312T-A35 target board using the ChipWhisperer-Husky-FPGA repository from GitHub (link: GitHub - newaetech/chipwhisperer-husky-fpga: FPGA design and test files for ChipWhisperer-Husky.).
During the synthesis process in Vivado 2022.2 with the Design Runs set to synth_no_ilas, I encountered several errors that halted the synthesis. Below are the key error messages:
ERROR: [Synth 8-448] named port connection 'fifo_rd_clk' does not exist for instance 'U_trace_top' of module 'trace_top' [C:/Users/t177h608/SCA/vivado/chipwhisperer-husky-fpga/fpga/hdl/cwhusky_top.v:1006]
INFO: [Synth 8-6157] synthesizing module 'fifo' [C:/Users/t177h608/SCA/vivado/chipwhisperer-husky-fpga/fpga/tracewhisperer/phywhisperer-common/hardware/hdl/fifo.v:25]
INFO: [Synth 8-6157] synthesizing module 'fifo_generator_0' [C:/Users/t177h608/SCA/vivado/chipwhisperer-husky-fpga/fpga/vivado/cwhusky.runs/synth_no_ilas/.Xil/Vivado-44924-JeanGrey/realtime/fifo_generator_0_stub.v:5]
ERROR: [Synth 8-6156] failed synthesizing module 'fifo_generator_0' [C:/Users/t177h608/SCA/vivado/chipwhisperer-husky-fpga/fpga/vivado/cwhusky.runs/synth_no_ilas/.Xil/Vivado-44924-JeanGrey/realtime/fifo_generator_0_stub.v:5]
ERROR: [Synth 8-6156] failed synthesizing module 'fifo' [C:/Users/t177h608/SCA/vivado/chipwhisperer-husky-fpga/fpga/tracewhisperer/phywhisperer-common/hardware/hdl/fifo.v:25]
ERROR: [Synth 8-6156] failed synthesizing module 'cwhusky_top' [C:/Users/t177h608/SCA/vivado/chipwhisperer-husky-fpga/fpga/hdl/cwhusky_top.v:25]
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Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2090.484 ; gain = 526.871
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RTL Elaboration failed
INFO: [Common 17-83] Releasing license: Synthesis
132 Infos, 34 Warnings, 0 Critical Warnings and 5 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
INFO: [Common 17-206] Exiting Vivado at Wed Mar 20 12:54:17 2024...
I tried resetting and generating output product for this specific fifo_generator_0 IP but it didn’t work.
Could anyone please advise on how to resolve these synthesis errors?