A minor example of trigger fluctuations

1 
int main() {
    platform_init();
  init_uart();
  trigger_setup();
//when I comment the my_read and do not write something before capturing, the trigger always times out
   char passwd[2];
    my_read(passwd, 2);
    trigger_high();
    
  
   int sum=1;
    int res=0;
    double n=5;
    for (double i = 0; i < n; i++) {
    for (double j = 0; j < n; j++) {
        // do some operation
        res*=sum;
    }
}
    final_result=res;
    trigger_low();

    return 0;
}

When n=5, trigger count is constant

int main() {
    platform_init();
  init_uart();
  trigger_setup();
//when I comment the my_read and do not write something before capturing, the trigger always times out
   char passwd[2];
    my_read(passwd, 2);
    trigger_high();
    
  
   int sum=1;
    int res=0;
    double n=10000;
    for (double i = 0; i < n; i++) {
    for (double j = 0; j < n; j++) {
        // do some operation
        res*=sum;
    }
}
    final_result=res;
    trigger_low();

    return 0;
}

Here when n=10000, the fluctuations occur.
I am using atxmega with UFO board and standalone CWLITE

This is my capture definition

def cap_pass_trace(pass_guess):
    reset_target(scope)
    num_char = target.in_waiting()
    #print(num_char)
    while num_char > 0:
        print(target.read(num_char, 10))
        time.sleep(0.01)
        num_char = target.in_waiting()
        #print(num_char)
    scope.arm()
    target.write(pass_guess)
    ret = scope.capture()
    if ret:
        print('Timeout happened during acquisition')

    trace = scope.get_last_trace()
    return trace

My scope details:
cwlite Device
sn = 50203220384d4a543030313135323035
fw_version =
major = 0
minor = 64
debug = 0
gain =
mode = high
gain = 30
db = 24.8359375
adc =
state = False
basic_mode = rising_edge
timeout = 2
offset = 0
presamples = 0
samples = 5000
decimate = 1
trig_count = 40
fifo_fill_mode = normal
clock =
adc_src = clkgen_x4
adc_phase = 0
adc_freq = 29538471
adc_rate = 29538471.0
adc_locked = True
freq_ctr = 0
freq_ctr_src = extclk
clkgen_src = system
extclk_freq = 10000000
clkgen_mul = 2
clkgen_div = 26
clkgen_freq = 7384615.384615385
clkgen_locked = True
trigger =
triggers = tio4
module = basic
io =
tio1 = serial_rx
tio2 = serial_tx
tio3 = high_z
tio4 = high_z
pdid = high_z
pdic = high_z
nrst = high_z
glitch_hp = False
glitch_lp = False
extclk_src = hs1
hs2 = clkgen
target_pwr = True
tio_states = (1, 1, 0, 0)
cdc_settings = bytearray(b’\x00\x00\x00\x00’)
glitch =
clk_src = target
width = 10.15625
width_fine = 0
offset = 10.15625
offset_fine = 0
trigger_src = manual
arm_timing = after_scope
ext_offset = 0
repeat = 1
output = clock_xor