ADC failed to lock when K16 set to 0 after loading bitfile

1

I am trying to run clock glitch on CW305. Here is the workflow:

First I set up the scope keeping J16 = 0, K16 = 1:


scope = cw.scope()
scope.gain.db = 25
scope.adc.samples = 200
scope.adc.offset = 0
scope.adc.basic_mode = “rising_edge”
scope.clock.clkgen_freq = 20E6
scope.clock.adc_src = “clkgen_x4”
scope.trigger.triggers = “tio4”
scope.io.tio1 = “serial_rx”
scope.io.tio2 = “serial_tx”
scope.io.hs2 = “clkgen”
```

then i upload bitfile

target = cw.target(scope, cw.targets.CW305, fpga_id=“35t”, force=True)

Then I set K16 to 0.

After that when I try to lock ADC:
target.vccint_set(1.0)

target.pll.pll_enable_set(True)
target.pll.pll_outenable_set(False, 0)
target.pll.pll_outenable_set(True, 1)
target.pll.pll_outenable_set(False, 2)

target.pll.pll_outfreq_set(20E6, 1)

target.clkusbautooff = True
target.clksleeptime = 1

if scope._is_husky:
scope.clock.clkgen_freq = 40e6
scope.clock.clkgen_src = ‘extclk’
scope.clock.adc_mul = 4

else:
scope.clock.adc_src = “extclk_x4”

for i in range(5):
scope.clock.reset_adc()
time.sleep(1)
if scope.clock.adc_locked:
break
assert (scope.clock.adc_locked), “ADC failed to lock”

It shows AssertionError: ADC failed to lock

If I set K16 = 0 before bitfile upload, then the capture does not see trigger. What should be the ideal workflow and what is wrong here?

2

J16 and K16 control clock connections. In our stock AES demo notebook, we instruct you to set J16=0, K16=1 and set scope.clock to source its sampling clock from the CW305-generated clock.

If you want to do clock glitching, then you cannot use the CW305-generated clock to supply the target clock; you must use the ChipWhisperer (Lite/Pro/Husky) to generate a glitchy clock, and have the target use that clock.

  1. You must keep scope.clock.adc_src to “clkgen_x4”, not “extclk_x4”
  2. You must set J16 to 1 to that the CW305 uses the CW-Lite-generated clock.
  3. You should set K16 to 0 so that the CW305 does not provide a clock back to the CW-Lite.
1 Like
3

@jpthibault thanks. After ADC lock, if I want to change the clock to non-glitched clock (clean clock) for a while then get back to glitch clock, what is the cleanest way to do that?

4

Normally the clock is glitchy at specific points in time, and outside of those times it is a clean clock; there is no need to switch to a different clock source.

If you haven’t done so already, you should go over our clock glitching notebooks (starting here) to learn the basics. Those notebooks do not use the CW305, but it’s the same principle.