AES 256 Oscilloscope Probing on CW305 FPGA target

I am running AES256 in CW305. Probing the amplified output X4 from the board, I got the following traces:

the smaller magnitude represents when the encryption is going on. Should it look like this? I don’t see the distinct spikes for 14 rounds of AES256 encryption. Should not that be visible here? I know there will be some noises but the 14 rounds should be visible/distinguishable i think.

It’s really hard to say without knowing the resolution of your X axis and your sampling rate. Can you also show the target trigger line, for reference?

I have taken data from oscilloscope and as you have suggested I plotted trigger as well. Below the first image a bit zoomed out. Green line is trigger and red line is probed trace

I see several spikes for trigger, 1, 2, 3. I wonder why trigger is behaving like this, spike 2 is confusing me if it really is a proper trigger or not. The next picture is zoomed in

I don’t understand if the encryption is going on between 1 and 2 or 1 and 3. whatever the case is, i am failing to see 14 rounds of operations.

  1. What is your sampling rate?
  2. What is the target’s clock rate?
  3. What is the trigger and why is it toggling all the time?

Is this a custom AES core, or is it our reference core modified as per this thread?

If it’s a custom core, I suspect that your trigger isn’t behaving as intended; I suggest you run a Verilog simulation to sort that out.

@jpthibault I have used the reference core with the settings mentioned in the thread. I was able to get a perfect probing once but can not reproduce it again. As I am not sure what is causing this, I thought I may have done something wrong so checked the AES128 probing using the default setup. The image is attached below:

For this image, sampling rate = 50k Sa/s, target’s clock = 10MHz, I have connected the trigger with TP1 as shown in CW305 whitepaper. This is the default AES128 provided by Chipwhisperer. Do you think this is correct trace? Its producing correct encryption.

You are sampling 50K times per second, but the target clock is toggling 10M times per second. You can’t expect to see anything useful with such a low sampling rate.

Since you are sampling asynchronously, you should be sampling several times faster than the target clock. 10x should be a good starting point (i.e. 100M Sa/s).