AES 256 Oscilloscope Probing on CW305 FPGA target

4
  1. What is your sampling rate?
  2. What is the target’s clock rate?
  3. What is the trigger and why is it toggling all the time?

Is this a custom AES core, or is it our reference core modified as per this thread?

If it’s a custom core, I suspect that your trigger isn’t behaving as intended; I suggest you run a Verilog simulation to sort that out.