I’m trying to do some clock and voltage glitching on a 32-bit implementation of AES. This one in fact: https://github.com/secworks/aes
And ‘readOutput()’ keeps returning all 0’s. My question is if readOutput() is looking at a specific pin that is simply not being set as the output, or what might be going on here. Thanks in advance for any tips.
I’m a little confused - the repo you linked is a Verilog implementation, which isn’t going to run on 32-bit platforms.
What are you using as a target board, and which target module are you using in the software? If you’re using the SimpleSerial module then the serial output might be going to the wrong place. I’d be happy to take a look at your firmware’s source code if you post it.
Oh, I see - when I hear 32-bit, I think of code running on a 32-bit CPU. Your setup makes sense too!
You’re using the CW305 target - how did you code the FPGA on it? Did you start with the example code from ChipWhisperer (ie: chipwhisperer\hardware\victims\cw305_artixtarget\fpga) or did you build it some other way? The Verilog source in that folder should show you how the pins need to be connected. I think you should be able to drop in this new AES in place of the Google Vault AES that’s there now. I’m also a total Verilog hack so I’m not entirely sure about all the details…
I tried plopping everything into the google_aes_vault and I thought it worked. But then when I looked closer I realized none of the files changed in the Vivado project, and when I try to change them there it breaks. So you have Vivado? Maybe I’m just doing something dumb and you could try doing the same thing real quick? If it’s not too much hassle that is.
I’ve got a few things on the go right now but I can try this when I get a chance! It may not be a straight drop-in replacement - I think the new AES module will have to be connected to the CW305 code the same way the current Google Vault code is, and setting up those connections might take a bit of massaging. I’ll let you know if I get anywhere.