Hi,
I am trying to get the aes128_verilog example running on a CW305. The Vivado project depends on the ila IP, which Vivado installations 2018.1 and 2020.1 won’t find.
Is ila the Integrated Logic Analyzer and where can I get this IP?
all the best.
Hi, yes you are right, these are Integrated Logic Analyzers.
First, you don’t need to re-run the implementation in Vivado, the bitfiles are already included in the ChipWhisperer releases.
If you really want to re-run the implementation, the easiest way to move forward is to simply undefine the ILA_* defines which trigger the ILAs’ inclusion:
Do leave the GOOGLE_VAULT_AES define, as shown above.
If you want the ILAs, you can easily generate them yourself in Vivado, just match the number of probes and width that you see in their instantiations.
Thank you. Just additional information, for those with similar issues, follow:
I learned that cryptosrc [1] (and others) also need to be placed according to the file structure in the chipwhisperer repository (in other words: aes128_verilog example is not self-contained). So be sure to checkout the entire chipwhisperer repository. After fixing this, I was able to run synthesis and implementation without errors.
BTW, Vivado 2018.1’s “Replace file…” does not work to replace missing files with actual files for me. Vivado crashed in my case.
Yep, you’re right. You can think of the directories under “vivado_examples” as the Vivado build areas, and source is pulled in from other places. Sorry for the confusion, happy to hear you’ve got it working. Vivado does have its “quirks”.
In case you haven’t seen it yet, you may find this appnote useful if you want to dive deeper on the CW305: http://media.newae.com/appnotes/NAE0010_Whitepaper_CW305_AES_SCA_Attack.pdf
Jean-Pierre
Feedback for this document (not sure where to put it otherwise): To the best of my knowledge, it should be “USB-B cable” whenever a “USB-A cable” is mentioned.
Oops, thanks for the note!
