Attacking Serial_based AES on an FPGA

1

I’d like to attack a serial_based AES using the “PA_HW_CW305_1-Attacking_AES_on_an_FPGA.ipynb” from the Archive.
But I get the following error:
AssertionError: Incorrect encryption result!

Is there anything that is needed to be changed for a serial AES in the process of capturing traces?

2

Hi,

A few questions:

  1. What do you mean by serial AES?
  2. If you’re using a custom bitstream, have you verified that it works?
  3. Are you using the same AES key as we use in that tutorial?
  4. Have you changed what registers in the FPGA things are stored in?

Alex

3

Hey :slight_smile:
Thank you for your reply.

  1. The AES which the plaintext and the key are loaded byte-wise to the module
  2. how can I verify that? I generated the bitstream using Vivado ( cw305_top as the top module )
  3. I didn’t modify anything in the tutorial but the bitstream
  4. Yeah, I modified my registers too.
4

The code in the CW305 demo should print what the ciphertext and expected ciphertext are. What do they print in your case?

Alex

5

AssertionError: Incorrect encryption result!
Got array(‘B’, [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0])
Exp [208, 202, 4, 78, 213, 104, 43, 181, 75, 95, 121, 178, 203, 94, 162, 61]

6

Yeah, either you’re not reading from the correct address on the FPGA (try using https://github.com/newaetech/chipwhisperer/blob/develop/software/chipwhisperer/capture/targets/CW305.py#L194)
or there’s something wrong with your bitstream (i.e. your design doesn’t work).

I don’t really know much about FPGA development, so I won’t be able to help you much there. I believe Vivado has a simulator you can use to help debug your design.

Alex

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7

We also provide a very basic testbench that you can easily run with “make” here:
https://github.com/newaetech/chipwhisperer/tree/develop/hardware/victims/cw305_artixtarget/fpga/vivado_examples/aes128_verilog/sim
You’ll have to install iverilog (and gtkwave to look at waveforms).
Of course you’ll have to adapt the testbench for any changes you’ve made to the target design.
Jean-Pierre

1 Like
8

Thank you for your replies. I managed to capture the traces by updating the cw_top level file.
( I added an always block to read the plaintext and key text and also pass the ciphertext)

9

Hi,

I am also trying to attack a serial implementation with CW following the same tutorial. I am getting the correct Ciphertext but for some reason there is no leakage in the traces. I presume this has got something to do with the ‘crypt_start’ signal. In the example design (which is a 128 bit implementation) this signal is passed to ‘load_i’ which I think marks the start of encryption.

When I map this signal to a similar port in my design the encryption doesn’t work. Could you please tell me how did you map this signal? Also, which serial implementation did you use?

Regards,
Ali

10

Are you using the CW305 for your target? If so the easiest way to sort this out is to adapt our basic Verilog testbench to your target (link two posts above). You want to see the top tio_trigger line going high when the encryption starts. Make sure your clocks are routed properly.

Jean-Pierre

11

Thanks for your reply Pierre. To the best of my knowledge, the trigger is configured properly. I have already measured the same design on a different setup. The only thing that I am concerned about is the influence of ‘crypt_start’ signal. What is its function? And is it necessary to incorporate it in the design or I can create a custom signal to enable the AES core?

Regards,
Ali

12

If you follow crypt_start in the Verilog source, you can see that it connects to the load_i input of the aes_core module, where it is used to kick off the AES operation.

There are a million ways to do this – best advice is to simulate the example target alongside your own target and verify that they behave the same way from a top black-box point of view. Alternatively, instantiate ILAs in your target and debug on the FPGA itself.

Jean-Pierre