I was wondering if there exists some form of de-facto baseline AES FPGA design that is used as a reference for comparison with other implementations, e.g. when implementing various SCA-resistant mechanisms. Are the CW FPGA implementations (for Spartan 6 on the CW308 and Artix 7 on the CW305 boards) completely in-house implementations, or are they adapted from a particular source?
I have no idea! My knowledge of different s-box implementations is limited to their optimization for size or speed. Typically, look-up table implementations are faster but larger – except on FPGAs, since FPGAs typically have lots of LUTs available “for free”.