My victim board normally has a 12Mhz clock, which is multiplied by 10 in its internal PLL, hence its main system clock is 120Mhz
This clock speed is far too high for the CWL’s scope, so I need to feed the victim with a slower speed clock.
Is there any way to use the glitch output to generate something like 3 or 4MHz, so I can slow down the victim to a speed at which the CWL scope will be usable ?
There’s one clock generator on the Chipwhisperer which is used to:
- Feed it to the victim through HS2 (pin 6 on the 20-pin flat ribbon cable)
- Go to a multiplier (x1 or x4) and serve as the frequency for the ADC
- Clocking the glitch module
The main issue you’ll be facing here is that the generated clock will also sync the ADC and the multiplier only goes up to x4 and it seems you would like to go to x10 here.
Unfortunately, if there is only one clock generator, this isn’t going to work for me, because the victim board’s firmware is using a 10x PLL multiplier. So using a x4 ADC multiplier will be sub sampling at 2.5x when at least 2x and preferably 10x + oversampling would be required on the ADC.
I presume that the FPGA would be capable of generating more clock signals, but installing the Xilix FPGA dev suite and reprogramming the FPGA just to add an extra clock, is far more work than simply building an external clock generator.
I have a AD9850 based DDS frequency generator module, which I can connect to a suitable MCU, or potentially just use a $2 STM32F103C8 dev board and use its hardware timer, to generate a integer division of its 72Mhz clock freq with minimal programming.
Its a shame that the CW doesn’t have a second independent clock generator from the FPGA, because most modern MCU’s operate on quite high frequencies with high clock multiplier PLL ratios; so the only way to use the CW ADC is to run the victim MCU at a lower clock frequency that its normal system clock.
I’m lucky this case because the victim board does not derive its USB clock from its system clock; but instead uses Clock Recovery from the USB signals themselves.
For a while I thought I’d need to implement my own , slow speed USB host system, but in this case, it looks like it won’t be necessary.
Anyway. Thanks again for the information, even though it was not what I was hoping for
Chipwhisperer was mainly designed for synchronous capture so this wouldn’t make sense to have 2 different base clocks.
What you would like is actually a broader range of internal frequency multipliers (instead of just x1 and x4) so that CW can feed the base clock to the targeted MCU while the ADC can sample at 10 times this clock in your case.
Not sure if there’s enough space left on the FPGA to add this feature though.