I want to reduce the adc_rate.When I set it like this"clock.adc_src = ‘clkgen_x1’ scope.adc.decimate = 600", the time to collect each trace increased from 0.04 seconds to 2 seconds. Could anyone tell me why this happend?
We don’t currently have feedback from the FPGA for when the capture is done, so we need to delay disarming the scope on the software side based on things like the offset/sampling rate/number of samples/etc. We’re delaying more than needed here, but we’re trying to prioritize capture always working over speed here.
Thank you very much for your reply！I want to know why it takes longer to collect a trace when I increase ’ scope.adc.decimate’.
Increasing the decimation will decrease
adc_freq, which increases the delay in
When I increase scope.adc.decimate, scope.clock.adc_freq don’t change,only scope.clock.adc_rate decrease.