ChipWhisperer Husky target board with L1 or L2 cache

[RajaKar]

I am using a ChipWhisperer Husky and would like to conduct cache-related experiments.

Are there any CW308 or CW312 target boards compatible with the Husky that contain:

• A conventional L1 instruction or data cache?

• An L2 cache?

• Separate L1 and L2 cache levels?

I looked at the CW312T-RP2350. My understanding is that the RP2350 has a shared 16 KB XIP cache for external flash access, rather than conventional per-core L1 instruction/data caches or an L2 cache. Please correct me if this understanding is wrong.

I also found that the i.MX RT1062 Cortex-M7 target may have separate L1 instruction and data caches. Is the CW308T-IMXRT1062 currently supported and recommended for cache hit/miss, and compatible with the Husky?

If no, then which target board is recommended?

Thanks.

[Alex_Dewar]

@RajaKar

I looked at the CW312T-RP2350. My understanding is that the RP2350 has a shared 16 KB XIP cache for external flash access, rather than conventional per-core L1 instruction/data caches or an L2 cache. Please correct me if this understanding is wrong.

I believe that’s correct.

@RajaKar

I also found that the i.MX RT1062 Cortex-M7 target may have separate L1 instruction and data caches. Is the CW308T-IMXRT1062 currently supported and recommended for cache hit/miss, and compatible with the Husky?

That target never left the beta stage, so I can’t comment on compatibility or functionality. We haven’t designed any targets for looking at L1/L2 cache. I’d recommend finding a device with a separate L1/L2 cache and either designing your own target board, or modifying a dev board for side channel analysis, though you may be getting into the territory where it may be easier to measure via an H-field probe or similar.