Custom AES core in CW305 fpga target

1

Hello! I have tried running AES256 in CW305 and was able to do it successfully. Now I want to run a custom AES core. in my core, I have the following inputs and outputs.

clk
i_text [text input]
i_key [key input]
rst_n [reset the core]
enable
trigger [when done encryption, trigger = 1]
o_text [ciphertext]

Now i am writing a state machine to drive that where i can provide key and text from chipwhisperer interface. But how do i tell my state machine that when I run cw.capture_trace(scope, target, text, key), it should then start from initial state each time?

below is my structure for state machine:

state_1 => reset
state_2 => initialize key, text
state_3 => enable = 1, if trigger == 1, go to state 4
state_4 => data_o = o_text

2

On the Python side, this is what eventually gets called when you run capture_trace(). As you can see it either toggles the usb_trigger Verilog input, or writes the REG_CRYPT_GO register. How you handle these in your state machine is up to you!

I recommend that you:

  1. Read the CW305 whitepaper.
  2. Run our Verilog testbench to understand how our example AES target works.