I plan to use a CW husky setup to reproduce results with “phase-modulation-sca-main/notebooks_capture/Baseline - Capturing T-Test and CPA with Shunt Resistor.ipynb” Script from (GitHub - colinoflynn/phase-modulation-sca: Resources to demonstrate phase modulation leakage including over JTAG).
Most of the functions return without error. The asynchronous data acquistion works fine.
The issue i have is when i try to take data in synchronous mode:
#syncronous - 120 MS/s ADC setting
def clocksetup(syncstr, fmcu, msps):
if syncstr == “sync”:
scope.clock.clkgen_src = “extclk”
scope.io.hs2 = None
if msps == 120:
print("fmcu =", fmcu)
scope.clock.pll.set_outfreqs(fmcu*1E6/2, 60E6, 2, True) ##input_freq, target_freq, adc_mul "External clock frequency is measured as 7.4 MHzsetting PLL to expect 15.0 MHz, so it may not lock."
elif msps == 60:
scope.clock.pll.set_outfreqs(fmcu*1E6/2, 60E6, 1, True)
else:
raise ValueError
elif syncstr == "async":
scope.clock.clkgen_src = "internal"
scope.clock.clkgen_freq = 60E6
if msps == 120:
scope.clock.adc_mul = 2
elif msps == 60:
scope.clock.adc_mul = 1
else:
raise ValueError
else:
raise ValueError
From this function is get errors from the function “scope.clock.pll.set_outfreqs(fmcu*1E6/2, 60E6, 2, True)”:
(ChipWhisperer Scope ERROR|File ChipWhispererHuskyClock.py:1242) Failed to update clkgen_freq: Could not calculate pll settings for input 7363636.363636363, output 7363636.363636363 with mul 1
Warning Traceback (most recent call last)
Cell In[71], line 2
1 scope.clock.adc_mul=1
----> 2 basetcapture(“sync”, 15, 60) # basetcapture(“async”, 15, 60) CAPTURES TRACES. No set_outfreqs error from pll
3 # TODO: sync and asyn and 60 msps and 120 msps
Cell In[62], line 4, in basetcapture(syncstr, fmcu, msps)
2 N = 100
3 print(“fmcu =”, fmcu)
----> 4 clocksetup(syncstr, fmcu, msps)
5 group1, group2 = capture_ttest(N, picoscope=False, splot=splot)
6 nptsave(“baseline{:d}mhz_{:s}_{:d}msps_ttest_10k”.format(fmcu, syncstr, msps), group1, group2)
Cell In[69], line 11, in clocksetup(syncstr, fmcu, msps)
9 scope.clock.pll.set_outfreqs(fmcu1E6/2, 60E6, 2, True) ##input_freq, target_freq, adc_mul “External clock frequency is measured as 7.4 MHzsetting PLL to expect 15.0 MHz, so it may not lock.”
10 elif msps == 60:
—> 11 scope.clock.pll.set_outfreqs(fmcu1E6/2, 15E6, 8, True)
12 else:
13 raise ValueError
File ~\ChipWhisperer\chipwhisperer\software\chipwhisperer\capture\scopes\cwhardware\ChipWhispererHuskyClock.py:675, in CDCI6214.set_outfreqs(self, input_freq, target_freq, adc_mul, force_recalc)
663 scope_logger.warning(“”"
664 Could not calculate pll settings for the requested frequency (%d);
665 generating a %d clock instead.
(…) 671 the target and ADC clocks; use at your own risk!
672 “”" % (target_freq, best_real_target_freq))
674 # set the output settings we found
→ 675 self.set_prescale(3, best_prescale)
676 self.set_prescale(1, best_prescale)
678 relock = False
File ~\ChipWhisperer\chipwhisperer\software\chipwhisperer\capture\scopes\cwhardware\ChipWhispererHuskyClock.py:420, in CDCI6214.set_prescale(self, pll_out, prescale_val, update_cache_only)
417 raise ValueError
419 if prescale_val == 4:
→ 420 self.update_reg(0x1E, 0x00, 0b11 << bitshift, msg, update_cache_only)
421 elif prescale_val == 5:
422 self.update_reg(0x1E, (1 << bitshift), 0b11 << bitshift, msg, update_cache_only)
File ~\ChipWhisperer\chipwhisperer\software\chipwhisperer\capture\scopes\cwhardware\ChipWhispererHuskyClock.py:219, in CDCI6214.update_reg(self, addr, bits_to_set, bits_to_clear, msg, update_cache_only)
217 if update_cache_only:
218 if not self._registers_cached:
→ 219 raise Warning(‘Registers are not cached: this is unexpected!’)
220 reg_big = self.cached_reg[addr][1]
221 reg_val = [reg_big & 0xFF, (reg_big >> 8) & 0xFF]
Warning: Registers are not cached: this is unexpected!
Can you provide hint to what goes wrong? Thanks in advance.