Does anyone has tried to use CW-Lite (breaked apart) with the SAKURA-G board ?
I noted that the CW-Lite 20-pin connector works at 3.3 V while the SAKURA-G at 2.5 V
In my particular case I only need to connect two signals between the boards:
1- A clock signal (48 MHz) from CW-Lite that feeds the SAKURA-G clock.
2- The trigger signal
You can send all the signals from the SAKURA-G to the CW-Lite, and the 2.5V signals will work OK at 3.3V levels. This means modifying the FPGA design to output a block on an appropriate pin (route to the CLKIN), and connecting the Trigger-OUT to GPIO4.
I can try to document this in more detail this weekend - traveling right now still so donāt have full lab setup.
Uhmmmm, at the first glance I was thinking that the SAKURA-G clock signal were generated by the CW-Lite (FPGA-HS2), then in this case the FPGA clock pin will se a 3.3 V inputā¦it is not harmful for the FPGA pin ?
Your approach implies that the ADC should be feeded by EXTCLK, right ?
Taking into account the electrical difference which approach is safer ?
Itās a lot safer to go from SAKURA-G --> CW-Lite, as otherwise you will see the issue w.r.t. different supply voltages.
For the SAKURA-G the clock actually comes from the ācontrolā LX9 FPGA. This is helpful as you donāt have issues with the output drivers of the target FPGA giving you a lot of noise on the power measurement.