CW-Lite Control of FPGA Signals for GPIO from Python API

Hello, new to the CW universe, but working on ramping up. Part of my motivation is to do research around microcontroller targets. Using the schematics for the CW-Lite-ARM, and reviewing tutorials and API docs, I see there are some ways to control a number of signals routed to the target, TIO1-4, and a couple others.

However, we’d like to have access to a couple more GPIOs in order to tickle the target. we’d also like to be able to POWER CYCLE (not glitch) the Target. I see that the Target Vcc is indeed switched, but was unable to find any reference to this in the API which might allow control. Further, to gain a few more GPIOs, I see there are signals related to the SmartCard socket. Might those be accessible to be used as “GPIO”? There also seem to be signals routed to J5.

For another facet of our work, we would like to perhaps operate a Target at a lower supply voltage, implying a lower VccIO for the FPGA. I note the TVREF pin on the 20-pin connector, but walking back into the CW-Lite portion of the schematic, I see SJ6. Is it correct that this must be opened, and instead pins 2 & 3 of JP5 be shorted in order to enable use of the external VREF signal provided on J1?

Also, it seems the PDID & PDIC signals come from a different IO-domain on the FPGA. Are these 3.3V IO Signals? Important to know as to whether we could use these as GPIO with a lower voltage Target (they come from the microcontroller?)

Finally a question on net names. On page 8 of the CW-Lite-ARM schematic, J1-pin8 is labeled VREF, while the net-name used elsewhere is TVREF. It appears as if the pin-names on J1 are part of the symbol. Is it safe to assume that the underlying net-names are as expected?

Thanks in advance for any insights that can be provided on these items.
Thanks also to the entire NewAE team for such an incredibly comprehensive system!

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You can disable/enable power on the target via = False / = True

All those pins go through the FPGA. You could modify the firmware for that, but the build is a bit tricky to get working, especially compared to our newer FPGA stuff. You could also try J7 and JP1, which go through the microcontroller, which is a much easier build.

I’d recommend just using level shifters instead. VREF there will only change the IO voltage for the FPGA and not the rest of the capture board, so setting a lower voltage there will probably cause issues between the FPGA and the onboard microcontroller at least. Quickly looking at the datasheets for stuff on the Lite, I think going down as low as ~2.4V on VREF might work, but I can’t guarantee it.

Yup, those are all 3.3V. I’m less familiar with the FPGA side, but it might be because they need to be bidirectional IO for programming XMega targets.

Yup, you should be all good there.


Thanks for the insights Alex!

Very Helpful!