A short field guide after getting the ATMega328P targets (CW304 Notduino and CW308T-AVR) capturing on a Husky Plus. A few of these cost me real time….
Build platform. Use PLATFORM=CW304. It is the ATMega328P / Notduino platform and it also covers the CW308T-AVR
Programmer. Select the AVR programmer explicitly: prog = cw.programmers.AVRProgrammer
Virgin fuse / clock (the one that hurt). A fresh ATMega328P ships with low fuse 0x62: internal RC at 1 MHz, external clock ignored. For side-channel work it must run off the Husky clock (external clock via JP8), so the low fuse has to become 0xE0 (external clock, CKDIV8 off).
on Husky Plus, AVRProgrammer(slow_clock=True) cannot program a virgin AVR. The ISP SCK stays too fast for a 1 MHz part and you get AVR-ISP Command 0x10 failed: err=0xc0.
Workaround: write the fuse once with an external ISP programmer through the ISP header, then never again.
avrdude -c usbasp -p m328p -U lfuse:w:0xE0:m
After that the part runs off the Husky clock and the Husky programs it normally at full speed. Do not connect the USBasp and the Husky at the same time (5V from the programmer can damage the Husky).
Serial pins are swapped. Notduino targets have TX and RX flipped versus normal targets. After default_setup():
scope.io.tio1 = "serial_tx"
scope.io.tio2 = "serial_rx"
Baud. basic-passwdcheck: 38400
Working setup (fuse already done):
SCOPETYPE = “OPENADC”
PLATFORM = “CW304”
CRYPTO_TARGET = “NONE”
SS_VER = “SS_VER_2_1”
VERSION = “HARDWARE”
scope.io.tio1 = “serial_tx”
scope.io.tio2 = “serial_rx”
target.baud = 38400
prog = cw.programmers.AVRProgrammer
cw.program_target(scope, prog, “../../../firmware/mcu/basic-passwdcheck/basic-passwdcheck-{}.hex”.format(PLATFORM))
Would be great to hear from NewAE whether the virgin-AVR ISP clock can be slowed on Husky Plus in software, or if it is fixed in the firmware/FPGA. Happy to share the full diagnostics…
AVR ISP clock (SCK) is too fast for a virgin part and cannot be slowed on Husky
cw version: 6.0.0
fw_version: {'major': 1, 'minor': 2, 'debug': 0}
sam_build_date: 09:22:46 May 26 2026
fpga_buildtime: 5/22/2026, 12:13
--- latest_fw / fw_version dict ---
latest_fw: {'major': 1, 'minor': 2}
latest_fw_str: 1.2.0
git log -1 --format="%h %ci"
2770d352 2026-06-01 21:29:40 -0400