Is there a way to adjust how fast the CW305 FPGA runs AES, and am I correct in thinking that leakage models would perform better at slower speeds? I’m having trouble capturing traces fast enough to be able to differentiate which part of a trace relates to the processing of the s-box operation for individual bytes. For example, in this image I’ve calculated and plotted the leakage for the first round s-box operation. There seems to be a correlation early on in the trace, but the CW-Lite scope is too slow relative to the FPGA to be able to capture the individual substitutions it seems, as all leakage spikes are overlapping. I’d appreciate your help!