The clock_and_resets block diagram looks correct (the clk_select.v and clk_wiz_0 modules don’t reside there, despite their names).
I’m puzzled that you keep getting this error. There are reports about this problem on the Xilinx support forum, but I’ve never run into it myself (despite instantiating clock wizard blocks in pretty much all of my projects), and I haven’t been able to find a nice clean solution from those who have encountered this.
One option to avoid this issue altogether is to use this earlier version of our DesignStart recipe, prior to the addition of the clk_select module. Functionally, all you will lose is the ability to bypass the PLL, which only matters if you’re interested in clock glitching.