CW305 bitstream file upload and vivado project constraints

Embedded Security ChipWhisperer Hardware
1

Hi,

I want to upload my own bit file to the CW305 target.
But to be sure, before I used mine first I tried the one that chipwhisperer’s own AES bit file which is “cw305_top.bit”. But I get this warning below and the LED4 is still ON so the FPGA is still unprogrammed. What am I doing wrong? (I read the Whitepaper_CW305_AES_SCA and the other questions on the forum but couldn’t figure this out)

cw305bit
cw305bit1171×151 14.1 KB

WARNING:ChipWhisperer Target:FPGA Bitstream not configured or '.../cw305_top.bit' not a file.

For my own vivado program, I would like to take input from the user via switches(on-on-off =1-1-0) and follow the output of the operations through LEDs so which ones should I choose to set as an input/output from the xdc.

thanks!

2

1- as the error message indicates, you haven’t specified a correct path for the bitfile. (remove the leading dash?)
2- the LEDs and switches are easy to find in the xdc (look for get_ports led1, and get_ports j16_sel…) But if I understand correctly what you’re trying to do, you don’t need to change the .xdc for that; you only need to change the Verilog source.

3

Thanks for the quick response
1-warning remains the same after removing the lead dash.
Actually copied the path directly from the jupyter URL:
[http://localhost:8888/edit/hardware/victims/cw305_artixtarget/fpga/vivado_examples/aes128_verilog/aes128_verilog.runs/impl_100t/cw305_top.bit]

And also tried to implement the cw305_top.bit that was copied somewhere else but the error was the same.

(http://localhost:8888/edit/hardware/victims/cw305_artixtarget/fpga/vivado_examples/aes128_verilog/aes128_verilog.runs/impl_100t/cw305_top.bit)

2-yes I wrote a verilog source for a simple operation and looked at the xdc, just wanted to know should I prefer any special LEDs or switches guess makes no difference :+1:.

4

Find your current directory by running !pwd, or if that doesn’t work:

import os
os.getcwd()

and either copy the bitfile there or provide a correct path from there to the bitfile.

5

Thanks used !pwd it turns out the pathname includes more than the URL (/home … etc.).

6

Hi, may I ask what was the complete pathname? And do you run all these commands just on any python environment?

7

@sasalamol were you able to program your bitfile? how did you make communication using chipswhisperer software with FPGA. I am a bit confused how should i structure my verilog codes to do that.

8

Hi, yes I did manage to program my bitfile. That is just the output of the vivado project. Than I placed that bitfile to a folder and in jupyter notebook for the chipwisperer software I specified the correct path to the bitfile. The board CW305 has 2 main chips on it one is the victim (FPGA) and the other is the controller (not an FPGA). If you use the chipwhisperer library (import chipwhisperer as cw) in python you can directly command the controller chip to take the prepared bitfile and put it in the FPGA (you can take a look at the picture above on my question), so you avoid a lot of extra work. Your verilog code doesn’t have to be structured for this process. Prepare your verilog code in any way that you want your FPGA to behave. I hope I explained it correctly.

1 Like
9

I dont remember the complete path name but the output after the !pwd command is the exact path if you are in the same folder with the bitfile.

I was using jupyter notebook to import chipwhisperer python libraries.

10

Hi Forgive me for not experimenting but I wanted help in implementing my own verilog code of combinations of some TDCs and AES 256, I have a bitstream file generated without CW305 xdc constraints. Is there any flow of how to now convert my project to one that can get dumped into CW305 and run. Please do share any resources or tutorials which helped you on this.
Thanks

11

We have lots of resources to get you going: