CW305 bitstream file upload and vivado project constraints


I want to upload my own bit file to the CW305 target.
But to be sure, before I used mine first I tried the one that chipwhisperer’s own AES bit file which is “cw305_top.bit”. But I get this warning below and the LED4 is still ON so the FPGA is still unprogrammed. What am I doing wrong? (I read the Whitepaper_CW305_AES_SCA and the other questions on the forum but couldn’t figure this out)

WARNING:ChipWhisperer Target:FPGA Bitstream not configured or '.../cw305_top.bit' not a file.

For my own vivado program, I would like to take input from the user via switches(on-on-off =1-1-0) and follow the output of the operations through LEDs so which ones should I choose to set as an input/output from the xdc.


1- as the error message indicates, you haven’t specified a correct path for the bitfile. (remove the leading dash?)
2- the LEDs and switches are easy to find in the xdc (look for get_ports led1, and get_ports j16_sel…) But if I understand correctly what you’re trying to do, you don’t need to change the .xdc for that; you only need to change the Verilog source.

Thanks for the quick response
1-warning remains the same after removing the lead dash.
Actually copied the path directly from the jupyter URL:

And also tried to implement the cw305_top.bit that was copied somewhere else but the error was the same.


2-yes I wrote a verilog source for a simple operation and looked at the xdc, just wanted to know should I prefer any special LEDs or switches guess makes no difference :+1:.

Find your current directory by running !pwd, or if that doesn’t work:

import os

and either copy the bitfile there or provide a correct path from there to the bitfile.

Thanks used !pwd it turns out the pathname includes more than the URL (/home … etc.).