CW305 External Clock


#1

Hi,
I would like to test the AES with a lower frequency (100 KHz) in the CW 305 FPGA board.
Can I use an external clock for the AES and then set the ADC to 4x sampling speed?

Thanks,
Ron


#2

Hi Ron,
You can use the external clock directly for the ADC but the lowest advertised supported frequency is 1 MHz… it seems to work ok down the 625 KHz, which is the lowest rate that the CW305’s PLLs seem to support.
In order to use EXCLK x4 sampling, the target clock needs to be at least 5 MHz.

What you could do is drive the Artix target with say 5 MHz, but then divide that clock inside the FPGA. You’ll have to dig inside the Xilinx documentation to see what’s possible there.

Hope that helps,
Jean-Pierre


#3

Hi Jean-Pierre,

Thanks a lot for your reply.
It seems that there is no easy solution to run the CW-305 lower than 1 MHz.

If anyone has a better solution or have used the FPGA at lower clocks, please let me know.

Thanks,
Ron


#4

Hi Ron,

A bit more on this, as I was a bit curious myself about what clock manipulations might be possible in the Artix7 target itself. It has a bunch of Clock Management Tiles, each of which has an MMCM and a PLL (Xilinx UG472 for all the details). In the Vivado IP catalog, find and launch the Clock Wizard to see how these can be configured… and unfortunately you’ll see that it doesn’t support output clocks below 4.687 MHz :frowning:

But what you could do is build a simple clock divider circuit, as per this thread. So, feed Artix7 a 1 MHz clock, divide it by 2 two or three times (in the Artix7). Make sure you declare the clocks you create in the process. Cross your fingers that the tool and the FPGA can support it (FPGAs have limited clock resources).

Curious to see if you get it working. Also curious why you’re interested in such a slow clock?

Regards,

Jean-Pierre


#5

Hi Jean-Pierre,

Thank you so much for your helpful responses.
I was trying to emulate the trace capture using a Spartan-3 FPGA, but realized that the sampling speed is ~1MSPS. So, I wanted to run the AES with a slower clock.

On that note, could you please let me know if there is an external pin on the FPGA which has the AES done pulse?

Regards,
Ron


#6

Hi Ron,

Assuming you’re using the CW305 AES example design, then I believe that the trigger output (IO4 on the 20-pin connector) goes high at the start of encryption and back low when it’s done.

Jean-Pierre