How can I set and follow an input text through the AES algorithm on the Verilog example project simulation?
Can I set the value directly from the simulation test bench?
Do I need to make any configurations for the simulation in order to get the correct results?
The input is set by the testbench here:
From what I can see on your simulation waveform it looks like a number of things are going (like the missing clock) so I’d look into resolving that first.
Does the “aes128_verilog.xpr” example include this tb.v simulation file or should I define them?
No, this simulation is run with “make” in the same directory where you find tb.v.
It’s possible to add the testbench to the Vivado project, but I vastly prefer running simulations with iverilog.
I’ve tried to use Icarus for the simulations but it’s my first time can you share the commands that I need to use?
I put the necessary files in the same directory with the iverilog, and entered the following command but I got these errors:
So what should I do to proceed?
Why don’t you just run
make compile? It calls iverilog with all the required arguments. In this case I think you’re missing