I am trying to capture traces with the CW305 aes128_verilog sample Vivado project. I changed the combination logic of the AES crypto core to something more simple and I can capture traces without issue. However, when I change the logic to include more gates, I get the OpenADC() timeout error. I believe the trigger is being driven by the top level module so changing the crypto core logic shouldn’t affect the capture traces.
No, the trigger is driven by the crypto core:
I did keep that assignment the same. I only changed the logic within the aes_core() module.
Then you should either run a simulation or use ILAs to see why
tio_trigger is not getting asserted.