CW305 OpenADC() timeout for AES sample project

myu8 · August 5, 2021, 2:09am

I am trying to capture traces with the CW305 aes128_verilog sample Vivado project. I changed the combination logic of the AES crypto core to something more simple and I can capture traces without issue. However, when I change the logic to include more gates, I get the OpenADC() timeout error. I believe the trigger is being driven by the top level module so changing the crypto core logic shouldn’t affect the capture traces.

jpthibault · August 5, 2021, 2:14am

No, the trigger is driven by the crypto core:

github.com

newaetech/chipwhisperer/blob/099807207f3351d16e7988d8f0cccf6d570f306a/hardware/victims/cw305_artixtarget/fpga/common/cw305_top.v#L246


   aes_core aes_core (
       .clk             (aes_clk),
       .load_i          (aes_load),
       .key_i           ({aes_key, 128'h0}),
       .data_i          (aes_pt),
       .size_i          (2'd0), //AES128
       .dec_i           (1'b0),//enc mode
       .data_o          (aes_ct),
       .busy_o          (aes_busy)
   );
   assign tio_trigger = aes_busy;
`endif


endmodule

`default_nettype wire

Jean-Pierre

myu8 · August 5, 2021, 2:20am

I did keep that assignment the same. I only changed the logic within the aes_core() module.

jpthibault · August 5, 2021, 2:22am

Then you should either run a simulation or use ILAs to see why tio_trigger is not getting asserted.