I’m working at a company that makes its own AES implementation in verilog. I wanted to pen-test that implementation and try different attacks on it.
To make things simpler, what I did was to take the working AES vivado project that comes with the tutorials and replace the ‘aes_core.v’ file with ours while keeping all the interfaces the same (input and outputs). It passed the synthesizing and implementation, generating bitstream and no timing errors whatsoever.
To simplify it even more, I am using the “Breaking Hardware AES on CW305 FPGA” tutorial the same way but with my new bitstream instead of the original project’s one.
The problem is that I can’t capture any traces and get the following output:
WARNING:root:Timeout in OpenADC capture(), trigger FORCED WARNING:root:Timeout in OpenADC capture(), trigger FORCED
I’ve been trying to change the PLL clocks but it didn’t work.
- Can you guess what the root problem might be?
- Is there any way to debug this? (I’m new to Vivado, some guidance would be appreciated)