CW noob looking for design / test artifacts for the FPGA on the CW312 target.
Found the Vivado project, but the simulations do not run. Looked through the repo and there isn’t a testbench for the ss_aes design found in …./firmware/fpgas/aes/hdl.
Am I looking in the wrong place or is there another way of simulating this design of this target?
I did find other testbenches for the CW305 variant of the design that uses USB, but the one I am looking to use uses a UART. Perhaps there is a wrapper that I couldn’t find that converts relevant USB traffic to UART?
Any pointers would be heavily appreciated
We have several different AES FPGA target implementations, supporting all our different target FPGA platforms, but they all use the same AES core inside; only the interface changes.
For simulation, we only provide a complete testbench for the CW305 variant, as you’ve found. This is all explained here. It is however the same AES core that’s used in the bitfiles that we provide for our CW312-A35 and -iCE40 FPGAs.
There is a testbench here for the SS2 wrapper, but this does not instantiate an AES core.
I think I figured out the answer I was looking for. I will write my own TB. If I have the time to dress it up, I’ll make it available, so that, if you like it, you can add it to the repo and folks like me can use it.