CWLite Sampling Question

I saw in the specs that the max ADC sampling rate for CWLite is 105MS/s.
So does that mean that it’s not recommended to do power analysis / glitching on any device running faster than 25MHz? (in order to achieve a 4x sample rate)
So in case of faster devices, I would need to remove the original oscillator and provide the clock signal myself through HS2

Hi @srmish,
Yes, with 4x sampling you would be limited to a target clock of 26 MHz. Now keep in mind that x1 sampling also works very well. But yes, if you have a target that runs at a faster clock rate you’d have to find a way of slowing it down.

Alternatively you could use an external oscilloscope alongside CW to capture samples, using CW for everything else (driving the target and doing the analysis). But if you take this approach you lose the benefit of synchronous sampling. (See this paper which shows how CW outperforms asynchronous sampling with external scopes at much higher sampling rates.)

Hope this helps,

Hmm ok interesting,
So you’re saying that if I’m doing synchronous sampling (AKA feeding the target’s clock into the CW’s HS1, or driving the target from CW’s HS2) then I might get away with sampling a 100MHz target (at 1x, naturally)

With x1 sampling you’ll likely need more traces, but it absolutely works. I think the paper I linked shows some results for that.
YMMV, but with the target I’m currently working on, with x4 sampling I break AES with 120 traces, and with x1 sampling it takes 400 traces.