Debugging Power Trace Collection on ChipWhisperer FPGA – Trigger Timeout Issue (no trigger seen)

Embedded Security ChipWhisperer Hardware
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I am trying to run Number Theoretic Transform (NTT) for Power Trace Collection on the ChipWhisperer FPGA board using my RTL implementation. However, I keep encountering the following error:

(ChipWhisperer Scope WARNING|File _OpenADCInterface.py:642) Timeout in OpenADC capture(), no trigger seen! Trigger forced, data is invalid. Status: 0b  
(ChipWhisperer Scope WARNING|File _OpenADCInterface.py:642) Timeout in OpenADC capture(), no trigger seen! Trigger forced, data is invalid. Status: 0a  
(ChipWhisperer Scope WARNING|File __init__.py:504) Timeout happened during capture  
Capturing traces: 100%|██████████████████████████| 1/1 [00:02<00:00,  2.14s/it]  
Failed to capture trace for iteration 0  
Captured 1 key and 0 traces.  
Shape of keys: (1, 32)  
Shape of traces: (0,)

To address this, I have attempted to mimic the signal flow of aes_core by passing NTT inputs through aes_pt, but I continue to receive the timeout error.

I am looking for debugging suggestions to ensure the trigger is correctly detected. Additionally, I would greatly appreciate a test bench for cw305_top.v to better understand how to provide inputs and integrate my own code so that the trigger functions correctly. Any help would be valuable!

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All of our example CW305 targets have a simple Verilog testbench, see e.g. chipwhisperer/firmware/fpgas/aes/README.md at develop · newaetech/chipwhisperer · GitHub

The way that triggering works is that the tio_trigger output of cw305_top.v must be raised when the target operation begins and lowered when it’s done.

1 Like
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Thanks a lot!
The testbench was instrumental in resolving the issue. Here are two key observations:

  1. The tio_trigger signal must be correctly assigned to the specific signal or region for which power traces are being collected. It should transition high when the region of interest is active and return low afterward.
  2. The aes_load signal should be connected to the algorithm such that each time it is asserted, the algorithm resets and starts execution from the beginning. Since aes_load is a one-clock-cycle pulse, it must be timed correctly to ensure proper triggering of the algorithm.