Documentation on modifying the CW's openadc specification

[viniul]

Hi!

I wanted to obtain “windowed” traces and seem to run into the exact same issue a person on this forum before me: Question about trigger high/low in CWLite firmware: short op - #3 by coflynn

The suggested in the issue is to change the verilog files:

@coflynn

To “fix” the issue, see the file app.assembla.com/spaces/chipwhi … p_stream.v at line 254 (might move in future versions), which looks like this:

.wr_en(adcfifo_wr_en & stream_write), // input wr_en

This is the write enable for the FIFO. You might be able to add another condition that only writes while the trigger condition is still valid

Is there any documentation on how to synthesize and flash the new specification onto the CW once I modified the respective verilog files?

Thanks!