Does CW305 firmware support bulk_mode?

[luffy]

Hi,

I tried to send 50 bytes data to “reg_crypt_k” in my CW305_ECC board, and the log is

At the same time, I use a vivado debug tool to read value in the CW305, however, the addr received by board is different with the send addr(0, 6, 0, 0)

When the “usb_addr” signal is supposed to be “21’h 000600(6, 0, 0 in (14+7) bits)” , the read value is “21’h 000000”

When I send 40 bytes, it behaves as expected

Therefore, I wonder that the bulk mode has been supported now? If so, what leads this error?

Thanks very much!

[jpthibault]

How are you doing the read/write operation?

BTW if you are using our example ECC target, then the “K” register is 256 bits / 32 bytes, so trying to read or write more than 32 bytes will result in undefined behaviour (it will probably wrap around, but there are no guarantees).

[luffy]

Sorry for not making the question clear.

@jpthibault

How are you doing the read/write operation?

I send data with

target.fpga_write(target.REG_CRYPT_K, text)

Sorry again, about the “read”， it was a typo, I was trying to convey the value I was getting from the debug waveform.

@jpthibault

BTW if you are using our example ECC target, then the “K” register is 256 bits / 32 bytes, so trying to read or write more than 32 bytes will result in undefined behaviour (it will probably wrap around, but there are no guarantees).

In the example ECC project, I’ve changed pKEY_WIDTH to 1024, so 50 bytes should be fine!

[jpthibault]

I added a simple 1024-bit register to the example AES projects and it works for me:

Be mindful of pBYTECOUNT_SIZE in Verilog, and ensure that target.bytecount_size has the same value.

Understand that when you do target.fpga_write(address, ...), address gets left-shifted by target.bytecount_size before getting put onto the FPGA address bus.

Also make sure your CW305 FW is up to date (target.fw_version_str should be 0.53.0).

[luffy]

Updating the firmware worked, thanks for the help!