Error Implement Design-Avnet_lx9board_ise

when I run the program, by default the top file is “clock_managment_advanced” That is correct?
It also shows me 3 mistakes, attached below.
error in implementation design—>.MAP


[code]Started : “Translate”.
Running ngdbuild…
Command Line: ngdbuild -filter “iseconfig/filter.filter” -intstyle ise -dd _ngo -sd coregen -nt timestamp -i -p xc6slx9-csg324-2 “clock_managment_advanced.ngc” clock_managment_advanced.ngd

Command Line: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\unwrapped\ngdbuild.exe -filter
iseconfig/filter.filter -intstyle ise -dd _ngo -sd coregen -nt timestamp -i -p
xc6slx9-csg324-2 clock_managment_advanced.ngc clock_managment_advanced.ngd

Reading NGO file “C:/Users/EDWARD/Desktop/CODES ADQUISICION/LO
GENERE4-LX9/Avnet_lx9board_ise/clock_managment_advanced.ngc” …
Gathering constraint information from source properties…

Resolving constraint associations…
Checking Constraint Associations…

Checking expanded design …

Partition Implementation Status

No Partitions were found in this design.

NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0

Writing NGD file “clock_managment_advanced.ngd” …
Total REAL time to NGDBUILD completion: 11 sec
Total CPU time to NGDBUILD completion: 11 sec

Writing NGDBUILD log file “clock_managment_advanced.bld”…


Process “Translate” completed successfully

Started : “Map”.
Running map…
Command Line: map -filter “C:/Users/EDWARD/Desktop/CODES ADQUISICION/LO GENERE4-LX9/Avnet_lx9board_ise/iseconfig/filter.filter” -intstyle ise -p xc6slx9-csg324-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o clock_managment_advanced_map.ncd clock_managment_advanced.ngd clock_managment_advanced.pcf
Using target part “6slx9csg324-2”.
Mapping design into LUTs…
Running directed packing…
Running delay-based LUT packing…
Updating timing models…
WARNING:Timing:3159 - The DCM, DCM_CLKGEN_inst, has the attribute DFS_OSCILLATOR_MODE not set to PHASE_FREQ_LOCK. No phase relationship
exists between the input clock and CLKFX or CLKFX180 outputs of this DCM. Data paths between these clock domains must be constrained
using FROM/TO constraints.
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
Running timing-driven placement…
Total REAL time at the beginning of Placer: 14 secs
Total CPU time at the beginning of Placer: 13 secs

Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:c626) REAL time: 15 secs

Phase 2.7 Design Feasibility Check
ERROR:Place:1205 - This design contains a global buffer instance, <adcclk_mux>,
driving the net, <systemsample_clk_OBUF>, that is driving the following
(first 30) non-clock load pins off chip.
< PIN: systemsample_clk.O; >
This design practice, in Spartan-6, can lead to an unroutable situation due
to limitations in the global routing. If the design does route there may be
excessive delay or skew on this net. It is recommended to use a Clock
Forwarding technique to create a reliable and repeatable low skew solution:
instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to
Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to
.C1. If you wish to override this recommendation, you may use the
CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
this message to a WARNING and allow your design to continue. Although the net
may still not route, you will be able to analyze the failure in FPGA_Editor.

ERROR:Place:1136 - This design contains a global buffer instance, <adcclk_mux>,
driving the net, <systemsample_clk_OBUF>, that is driving the following
(first 30) non-clock load pins.
< PIN: systemsample_clk.O; >
This is not a recommended design practice in Spartan-6 due to limitations in
the global routing that may cause excessive delay, skew or unroutable
situations. It is recommended to only use a BUFG resource to drive clock
loads. If you wish to override this recommendation, you may use the
CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
this message to a WARNING and allow your design to continue.

Phase 2.7 Design Feasibility Check (Checksum:c626) REAL time: 15 secs

Total REAL time to Placer completion: 15 secs
Total CPU time to Placer completion: 15 secs
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

Mapping completed.
See MAP report file “clock_managment_advanced_map.mrp” for details.
Problem encountered during the packing phase.

Design Summary

Number of errors : 3
Number of warnings : 1

Process “Map” failed
[/code] :frowning:

Hi Edward,

Not sure what happened - the top-level file should be “openadc_inverface.v”. I’ll try to recreate the basic LX9 project to confirm there are no errors… sometimes errors occur in later versions of the ISE tools then I originally tested with.

If you run the ‘makeprojects_win.bat’ in openadc\hdl\example_targets it should generate a .xise file in avenet_lx9board_ise that is configured as you need.

[size=150]I have the ISE Design Suite 14.7. I run the ‘makeprojects_win.bat’ in openadc \ hdl \ example_targets .xise it and generated a file in avenet_lx9board_ise.
but the file is set as top “clock_managment_advanced”.
I’m using files in the folder chipwhisperer-0.07.
when I try to change the top file, leaving many errors.
I would put photos but I can not copy and paste .JPG files this way.[/size]

If you hit “Full Editor” it should allow you to attach photos. I’m not sure what happened, as using ISE 14.7 I could open the file and it looked correct (as attached photo shows).

I’ve included a copy of my repo, with that project made. ISE should ask you to regenerate the cores too when you run the “generate bitstream” function. (3.67 MB)

OK, the file is generated .bit correctly.
Now I open the Python file [“adc-cpture-example”] and I get the following message:

(<type ‘exceptions.ImportError’>, ImportError (‘No module named FTD2XX’) <traceback object at 0x03B64AD0>)
FTD2XX import failed. Install XXX from XXX for FTDI support

what should I do?

Hi! What is USB chip used? FX2 or FT2232? I think , if you not use FT2232 it is normal message.

Yeah… that’s really just a “warning” sorry about that! If you don’t use the FTxxx you can very safely ignore that.

You need to plug in the USB-Serial cable (micro-usb on LX9 board) and ensure the drivers for it are installed, then point the Capture software to that port.

connect the micro-USB cable to board LX9 select COM3 and showed me the following error.:


Is D3 led on the board flashing and D2 on constant? The “timeout in read” makes it seem like it’s having trouble communicating at all.

yes, ahy flickering of the LEDs. Flash memory recording in the “openadc_lx9.mcs” file. as it must be the acquisition of hardware ?.
I have this design

I look in your design you use the external clock signal and trigger signal
however the only entry that I have is the input signal, I don’t have external clock signal , Idon’t have trigger signal, I think that’s the reason for the errors.
that signals python expected to acquire data?
python expected external clock signals and trigger signal?
as I can solve and make the acquisition? :frowning: :frowning:

signals that Python expects the acquisition to start?
that signals LX9 expected to begin saving data every 32 K and send it through serial protocol :unamused: :unamused:

Hi, I have been reading the manual OpenADC card and I don’t understand ESD ? what is it?.
According to the manual I just need OpenADC and LX9. but I can’t acquire the signal yet, which believes that the next step would be to continue to try to save the data.
has been recorded file in memory .mcs however Python can not acquire data.
I think python expected trigger and clock signal as I solve this problem?
I need another circuit ??
According to what I can see you use the atmega, in my case I need to use a similar circuit ??, although the OpenADC manual never mentions. :confused: :confused: :frowning: :frowning:

Hi Edward,

Sorry on the delay - just wanted to respond still going to double-check the design in repo is working. Was going to do that today, we had a long weekend here so just getting back to the lab now, will do that asap!

Hi Edward,

I was able to do the following:

  1. Clone the GIT repo (fresh clone)
  2. Put the ‘sfutil.exe’ binary into the location, run the ‘program_flash.bat’ file in same location (openadc\hdl\example_targets\avnet_lx9board_docs)
  3. Plug in USB-Serial cable, wait for driver install.
  4. Run the ‘’ script.
  5. Connect to given USB port.
  6. Press the capture button and get a signal.

I’m not sure why this fails. By default you don’t need any external signal to get a basic waveform displayed!

You also don’t need to worry about the XMEGA… it’s used for JTAG on the LX9 board. I don’t have code for it (its not open source) and you should leave it programmed as it came for full functionality. I only use the serial port on the LX9 board.


Put the ‘sfutil.exe’ binary into the location, run the ‘program_flash.bat’ file in same location ()(openadc\hdl\example_targets\avnet_lx9board_docs)

This is done after or before recording the .mcs file?
also runs stutil.exe?

when already recorded .bit file, the LED D2 lights up continuously but the D3 LED flashes. :confused: :confused:
run the bitmap python and stops working (error)

:frowning: :frowning: :blush: :blush:

.mcs recorded the file and the LED 3 flashes and the LED 2 is constantly on recorded is it correctly?
I need to get the signal as soon as possible, is there any other way to get out of this mess? :cry: :cry:

I’m using Window 8
what operating system that you perform the tests?
if I install python on linux, would have better results?, help me with adquitition ;( :confused:

Hi Edward,

Hmm… I’m using Win 7, but Win 8 “should” work? There may be some issue with the serial driver! I’ve had a lot of trouble recreating the same problem, have been out of office past few weeks so just getting back into things now.

Linux should work - but have you tried the “ChipWhisperer Instant” virtual machine? That would save you from installing everything… the OpenADC code would be in the ~/chipwhisperer/openadc directory (you can ignore the ChipWhisperer stuff). You need to add the username to the “dialout” group, via a terminal this can be done with:

sudo usermod -a -G dialout cwuser

If it’s still giving trouble and you want to return the OpenADC let me know too (email is easiest then probably,! Not sure why things don’t seem to be working!