Hi, I have been researching with the ECC SCA attacks (SCA 04) specifically using CW 1200 with CW305 FPGA. Most attacks are on the P-256 curve. I would to explore more curves with higher bit width.
I know I have to change the implementation to accumulate this additional bits.
Seeing how complicated the verilog is , I wanted to your opinion about this.
Is it possible to change the bit length of k from 256 to 288 bits?
Really appreciate any inputs on this. Thank you very much.
for my research purposes, I
I cannot help you there because we didn’t write the target ECC implementation used in sca204; we borrowed it from here. There you will find 384-bit ECC implementations (which we have not looked at).
I will say two things:
- Implementing cryptography is notoriously hard to do correctly (especially with regards to resisting side-channel attacks), so changing the curve size may not be trivial at all.
- For the type of attack that we used, increasing the number of bits doesn’t necessarily make the attack harder; actually the opposite may be true.
Thank you for your input, I appreciate it.
If I may trouble you with another question.
The Artix-7 FPGA on CW305, has a set constraints and definition of register for the 256 bits only. Does the FPGA have any additional registers that could be used to increase the bit length or would 256 be the maximum that is possible?
256 is not the maximum. Read about the pBYTECNT_SIZE parameter in the CW305 appnote. Here it is set to 8 which means that each register may be up to 256 bytes long.