Generate bit flie in CW305_ECC

Understood, can I ask about how to connect cw305 board through vivado? Because my vivado can’t connect myboard successfully.

How is the CW305 connected to your PC?
In order to connect from Vivado, you need something like this connected to the CW305’s “FPGA JTAG” header (lower-right corner).

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Hi I noticed that ecc encryption in the curve_mul_256.v is 32 bits input and 32 bits output, but in my design I want to use 256 bits input and 256 bits output, is it work?
Because I see vivado synthesis, it didn’t synthesis the
input wire [255:0] brom_g_x_dout;
input wire [255:0] brom_g_y_dout;

and in the cw305_reg_pmul.v, it didn’t synthesis the
output wire [255:0] O_k_word,
output reg [255:0] O_gx_word,
output reg [255:0] O_gy_word,


Again, the internal data path width is an implementation choices which is completely irrelevant to a functionally correct implementation.

Vivado (or any other synthesis tool) will remove any logic that is determined to not have any effect on top-level outputs. If you look at the synthesis log files, you will see messages indicating this. So it looks like your problem is a Verilog problem, not a CW305 problem.

If you can share your complete Verilog source code I can have a quick look to see if anything jumps out, but I can’t tell anything from those screenshots.


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Hi, thank you for your help.
Here is my design ECPM.v that I use this to replace curve_mul_256.v
also I modify something in cw305_ecc_p256_pmul_top.v and cw305_reg_pmul.v (13.3 KB)


What I can see in this source code looks fine.
The first thing I would check is whether the ECPM module is getting its clock (crypt_clk).
Are the red and green LEDs on the CW305 board flashing?

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Yes, they are flashing after I input the .bit file.

Hi, I successfully fix the synthesis didn’t match my RTL logic error through the warning message in synthesis(multi-driven and latch), thank you for your help.
Now I’m still working on LUTs number exceed the maximum LUTs of CW305 35T