Hello i have simply question , lets say about my DUT is executing instructions at 300mhz clock and if i want to glitch them by vcc crowbar i need exactly 300mhz ( 3.3333333333333 ns) vcc glitch width ? whats happend if i generate 150mhz or 50mhz glitch ? these instructions would not be glitcheable or ill glitch more than 1 instruction executed at 300mhz clock in one time ?
I wouldn’t really relate the glitch width to the number of instructions you glitch. It’s not necessary to match your target clock to the glitch clock.
So far I’ve found that setting the glitch width to a multiple of the target’s clock period works best.
ok thx for explain
i have another question via jupyter notebook on cw-lite i can use externall signall like 1/0 to trigger the glitch with speciffic delay but is there possibility to do automatic delay incrementation on every 1/0 trigger signal via python ? or i must modiffy fpga code to add this functionallity ?
That would be easy to do in Python I think. As you need to arm the scope for each glitch, you can as well change any parameter, including width and ext_offset.
def glitch(repeat, offset): scope.glitch.repeat = repeat scope.glitch.ext_offset = offset scope.arm() trigger() ret = scope.capture() # Reset MOSFETs here # Get result and so on