I am starting to work with the CW305 Artix board. My final goal is to run my own VHDL designs on it and assess their side-channel security. However I will not be using CW devices for the trace acquisition, but just a normal oscilloscope. I was wondering if there is any step by step guide on the installations steps for the CW305 Artix board and for how to upload some test bitstream.
but in Section 4 I didn’t quite get which steps were necessary for running code on the board and which steps were necessary for communicating with the other devices. I.e. which guidelines should we follow if we are only using the target board and nothing more?
You can connect to the CW305 using Python like it shows in section 5; since you don’t have a CW “scope”, replace the scope argument with “None”:
import chipwhisperer as cw
target = cw.target(None, cw.targets.CW305, "/path/to/bitstream", force=True)
Then you can use the CW305 target methods (i.e. all target.* methods discussed in the app note, like the target.pll.* calls).
For sending/receiving data to/from the FPGA, have a good look at section 8 if you want to follow our standard way of doing that (which would allow you to use the target.fpga_read() and target.fpga_write() methods). (While we named this section “porting your own AES core”, it applies to any target core, not just AES.) You might find it helpful to run the simulation testbench to “see” how it all works.
Hello again JP,
I was trying to run target = cw.target(None, cw.targets.CW305, “/path/to/bitstream”, force=True) with the corresponding path which seems correct. However for the target command I get the following TypeError:
target() takes from 1 to 2 positional arguments but 3 were given.