I need to raise the ADC clock speed to 8*7.37MHZ in my CW-Lite. I tried to change the scope.clock.clkgen_freq variable to 89.6e6 but it did not work. I suppose I need to change the baud rate of the serial communication; however, I do not know where that might be. Can you help me, please? Do I have to flash a new firmware for changing the baud rate?
Are you trying to clock the ADC at 8 times the target clock speed, or are you just trying to clock it at 8 times 7.37MHz? The former is not possible with the current FPGA firmware. It may be possible if you update the FPGA code and build new firmware, but I’m not sure.
You can change the target baud rate by
target.baud = 38400. With the same firmware, you will need to multiply it by the same ratio that you changed the target clock speed by.
Thanks for the quick reply. Since the target is working at 7.37Mhz, I was thinking to boost the ADC clock 8 times to get more samples in each clock the target executes an instruction, but the DCM module won’t let me to do that and it only supports X4.