How should CLK glitch look on logic analyzer view?

I had some trouble CLK glitching STM32F4 (STM42F3 worked), so I looked at the output of the Chipwhisperer’s clock signal thinking that the F4’s clock is probably too fast, so I need some extra FPGA for faster glitches.

What striked me odd is that the CLK output signal from Chipwhisperer’s HS2 looks too regular (used up to 400 MHz sampling on logic analyzer; 8 MHz as the clock frequency) and I couldn’t find where the glitches are, even if I put repeat count of 100 or more. More strangely, I thought that using “glitch only” setting would allow me just to see the pattern of glitches somewhere without it being XOR-ed with normal clock.

However no matter what the setting, I couldn’t find the glitch pattern in the logic analyzer’s view.

How much time should I expect the glitch pattern to be offset from the time the trigger is triggered? (I can attach resulting waveform, but need to know how far away from trigger to expect the glitch if offset after trigger is set to 0)

OK there was a mistake when I used manual settings (script worked, but forgot a setting in the IDE).

To answer my own questions these are how the generated glitches look like (channel 0 is CLK, channel 2 is trigger, one is CLK xor-ed, other glitch only):