How to correctly calculate phase shift steps?

Nidrnox · May 26, 2026, 7:12pm

Hello,

during some analysis of my data of clock glitch parameter sweeps utilizing the glitch controller on a Husky, i wondered, how exactly the value of scope.glitch.phase_shift_steps is generated.
During my research i came across these lines in the source code(?) in GitHub referring to the Xilinx documentation, as well as the formula of 56 * (FPGA VCO freq / clock freq) on page 9 of this paper.

However, in my jupyter files, I have the following output:

scope.cglitch_setup()
print(f"pss: {scope.glitch.phase_shift_steps}")

scope.adc.samples                        changed from 130000                    to 5000                     
scope.adc.clip_errors_disabled           changed from True                      to False                    
scope.adc.lo_gain_errors_disabled        changed from True                      to False                    
scope.clock.adc_mul                      changed from 8                         to 4                        
scope.clock.adc_freq                     changed from 58909090.90909091         to 29454545.454545453       
scope.clock.adc_rate                     changed from 58909090.90909091         to 29454545.454545453       
scope.io.hs2                             changed from glitch                    to clkgen                   
scope.glitch.enabled                     changed from True                      to False                    
scope.glitch.mmcm_locked                 changed from True                      to False
pss: 4592

A clock frequency of 29.45 MHz and 4592 phase shift steps would result in a FPGA VCO frequency of 2.41 GHz, which is double than the in the documentation defined value of the PLLs maximum operating frequency. How can this be?

Unfortunately I currently have no access to the hardware, to just control the FPGA VCO frequency myself.

Thanks for any help and explanation and all the best

Nidrnox

jpthibault · May 26, 2026, 7:56pm

Welcome! All glitch logic runs from the target clock, not the ADC clock.

In your case here, this clock is 4x lower than your ADC clock. Which brings us back within the legal VCO range.

In case you haven’t seen it, this notebook explains some of this in more detail:

github.com/newaetech/chipwhisperer-jupyter

demos/husky/03%20-%20Husky%20Glitching.ipynb

main

{
 "cells": [
  {
   "cell_type": "markdown",
   "metadata": {},
   "source": [
    "# CW-Husky glitch exploration\n",
    "\n",
    "CW-Husky's FPGA includes a small logic analyzer which allows the glitch generation to be visualized. This can be helpful to understand how the glitch parameters influence the shape of the glitch.\n",
    "\n",
    "The glitch signals captured in this notebook are digital FPGA internal signals; if you're interested in the actual shape of the glitch output, you won't get that from this; you'll need a good analog oscilloscope instead.\n",
    "\n",
    "No target needs to be connected for this notebook.\n",
    "\n",
    "If you don't have a Husky, you can still use this notebook to understand how Husky generates glitches; skip down to the \"If you don't have Husky\" section. Skip over all the preceding cells.\n",
    "\n",
    "This is also a companion to test_husky.py, for when visual inspection of glitches is needed."
   ]
  },
  {

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Nidrnox · May 26, 2026, 8:20pm

Seems like I mixed up the clocks.

Thank you very much for the quick reply!